With the scaling of integrated circuits, metal-oxide-semiconductor (MOS) devices become increasingly smaller. The junction depths of the MOS devices are also reduced accordingly. This reduction causes technical difficulties during the formation processes. For example, small MOS devices demand higher dopant concentrations in source and drain regions in order to reduce resistivity in the source and drain regions. Controlling implantation depth for forming shallow junction in source and drain extension regions of small-scale devices is also difficult.
To solve the above-discussed problems, raised source and drain regions and/or raised lightly doped source and drain (LDD) regions have been formed. FIG. 1 illustrates a commonly formed MOS device having raised source/drain regions. In its formation, a gate stack including a gate dielectric 4 and a gate electrode 6 are formed on substrate 2. LDD regions 8 are then formed by implantation. Gate spacers 10 are then formed. An epitaxial growth is then performed to grow a crystalline silicon layer 12 on substrate 2. Source and drain regions 14 are then formed by an implantation.
FIG. 2 illustrates a MOS device with raised source and drain regions and raised LDD regions. A typical formation process includes forming offset spacers 16 on sidewalls of a gate stack including gate dielectric 4 and gate electrode 6, epitaxially growing a first silicon layer 18 on substrate 2, implanting impurities to form LDD regions 8, forming main spacers 10, epitaxially growing a second silicon layer 20 on first silicon layer 18, and implanting impurities to form source and drain regions 14.
In the conventional formation processes as shown in FIGS. 1 and 2, raised regions for PMOS and NMOS are typically formed simultaneously, and thus comprise the same materials. This process incurs several problems. First, since LDD regions are formed prior to the epitaxial growth, the epitaxial layers in PMOS and NMOS devices may have different thicknesses resulting from the different impurities in PMOS and NMOS devices. Second, epitaxial growth of silicon typically requires high temperatures, and thus excessive diffusion of dopant degrades short channel performance of the MOS devices. Further drawbacks include low activation rates and low solubilities (since impurities are implanted), and high silicide contact resistance, which results from the low activation rates and low solubilities of impurities.
What is needed in the art is a MOS device that may incorporate raised source and drain regions and/or LDD regions in order to take advantage of the benefits associated with improved MOS device performance while at the same time overcoming the deficiencies of the prior art.